Sigma-delta modulators or sigma-delta modulation (both of them hereinafter referred to as SDM) are recognized as proven methods that are extensively employed in high-resolution data conversion applications. They simultaneously utilize noise shaping and oversampling techniques to reduce the quantization noise power within the input signal bandwidth, achieving higher resolution and linearity compared to a Nyquist-rate data converter. Because of the oversampling requirement, however, SDMs have been employed in relatively low bandwidth applications such as digital audio, voice, ISDN (Integrated Services Digital Network), and instrumentation applications with nearly excellent results. With the recent developments in Very Large Scale Integration (VLSI) technologies, SDMs have become attractive in relatively wide bandwidth applications, as well. Essentially, the constant evolution in video technologies (such as HDTV), and wireline communication services (such as xDSL) and wireless communication systems (such as 3G and 4G mobile communication standards) increasingly demands higher-resolution and wider bandwidth from an SDM data converter.
An exemplary SDM includes a quantizer in a negative feedback configuration to spectrally shape the quantization noise away from the input signal spectrum. The number of levels of the internal quantizer used in an SDM is usually two (i.e., a single-bit quantizer). Single-bit SDMs have found widespread applications due to their inherent linearity and simplicity. One drawback of at least some single-bit SDMs, however, is that to obtain a higher resolution or wider bandwidth, a higher-order feedback loop is used, which in turn can cause stability problems and significantly reduce the maximum allowable input range. Also, the required oversampling ratio (OSR, where OSR is defined as the ratio between the sampling rate of the output to the two times the input signal bandwidth) can be high, limiting the achievable maximum input signal bandwidth (because of the maximum attainable sampling frequency in a given VLSI technology). The use of a multi-bit quantizer within an SDM (i.e., a multi-bit SDM) offers wider bandwidth and higher-resolution with improved stability and reduced OSR, and therefore is desirable in wide bandwidth and high-resolution applications such as emerging video and wireless communication applications mentioned above.
Notably, however, in multi-bit SDMs, the multi-bit Digital-to-Analog Converter (DAC) within the feedback path preferably has the same linearity requirement as the overall SDM Analog-to-Digital Converter (ADC). Any non-linearity introduced in the feedback path of the SDM directly appears at the system output, without undergoing suppression provided by the feed-forward loop filter. Therefore, component mismatches in the multi-bit feedback DAC can severely limit the achievable resolution. For instance, if a three-bit SDM ADC is designed to achieve a 16-bit resolution, then the three-bit feedback DAC preferably also has 16-bit linearity (though the number of bits in the feedback DAC is three) so that it does not produce any undesirable effect on the ultimate performance. Achieving 16-bit linearity from a multi-bit DAC in digital Complementary Metal-Oxide Semiconductor (CMOS) technologies can be difficult unless expensive laser trimming or calibration techniques are used. For this reason, multi-bit SDMs are known to be very sensitive to the tolerance of standard CMOS technologies. To tackle this problem, various algorithms, which are collectively referred to as the Dynamic Element Matching (DEM) techniques, have been developed in the literature.
Several first-order DEM techniques have been proposed, such as DEM based on the random selection of unit elements in the feedback DAC, based on Individual Level Averaging (ILA), and based on Weighted Averaging (DWA). Each is described further below.
An exemplary DEM method based on the random selection of unit elements in the feedback DAC was proposed by L. R. Carley in “A noise-shaping coder topology for 15+ bit converters,” IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 267-273, April 1989, which is hereby incorporated by reference. Another exemplary DEM method, termed Individual Level Averaging (ILA), was proposed by B. H. Leung and S. Sutarja in “Multi-bit sigma-delta A/D converter incorporating a novel class of dynamic element matching techniques,” IEEE Transactions on Circuits and Systems. Analog and Digital Signal Processing, vol. 39, pp. 35-51, January 1992, which is also hereby incorporated by reference. In the ILA approach, unlike the random DEM method, the selection of unit elements is decided with a digital logic that incorporates a memory storing the information regarding whether a particular unit element was used in the previous clock cycles or not. The memory feature of the ILA makes this method more efficient since the usage of each unit element can be made more uniform.
In the DWA technique, the unit elements are selected in a circular way, and, therefore the noise arising from the mismatches among the unit elements is spectrally shaped by a first-order high-pass transfer function. For example, the DWA approach is further discussed and proposed in an article by R. T. Baird and T. S. Fiez, entitled “Linearity enhancement of multi-bit delta-sigma A/D and D/A converters using data weighted averaging,” IEEE Transactions on Circuits and Systems: Analog and Digital Signal Processing, vol. 42, pp. 753-762, December 1995 (which is hereby incorporated by reference). The DWA approach can provide a significant improvement over the randomization DEM and ILA techniques since the mismatch noise is spectrally shaped.
A Data Directed Scrambling (DDS) technique has also been proposed to provide a first-order spectral shaping of the mismatch errors. See, for example, U.S. Pat. No. 5,404,142, entitled “Data-directed scrambler for multi-bit noise shaping D/A converters,” which is hereby incorporated by reference. The DDS approach can provide a first-order spectral shaping of the mismatch errors. In the context of SDMs, however, achieving a higher-order mismatch-shaping DEM is important because the mismatch errors introduced by the multi-bit feedback DAC can be better suppressed within the input signal bandwidth in the same manner as it is done for the quantization noise.
Several higher-order DEM techniques have been proposed, such as in U.S. Pat. No. 6,266,002, issued in July 2001 to X. M. Gong, E. Gaalaas, and M. Alexander, entitled “Second-order noise shaping dynamic element matching for multi-bit data converter;” U.S. Pat. No. 5,986,595, issued in November 1999 to C. Lyden; A. Keady, entitled “Reduction of mismatch errors for multi-bit oversampled data converters;” R. Schreier and B. Zhang, “Noise shaped multi-bit D/A converter employing unit elements,” published in Electronics Letters, vol. 31, pp. 1712-1713, September 1995; J. Welz, I. Galton, and E. Fogleman, “Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters,” IEEE Transactions on Circuits and Systems: Analog and Digital Signal Processing, vol. 48, pp. 1014-1028, November 2001; A. Yasuda and H. Tanimoto, in “Noise shaping dynamic element matching method using tree structure,” Electronics Letters, vol. 33, pp. 130-131, January 1997; and A. Keady and C. Lyden, in “Tree structure for mismatch noise-shaping multi-bit DAC,” Electronics Letters, vol. 33, pp. 1431-1432, August 1997. Each of the above references is hereby incorporated by reference.
In some cases, known conventional methods have been limited to second-order mismatch-shaping due to difficulty and complexity in the design of higher-order mismatch-shaping algorithms. In addition, the second-order mismatch-shaping can suffer from digital hardware overhead. The hardware complexity of the second-order mismatch-shaping DEMs scales exponentially with the number of unit elements in the feedback DAC. The extension of the second-order mismatch-shaping DEM to third and higher-order cases has problems due to the stability issues in the mismatch-shaping algorithm, and requires complex hardware, as described in the prior art.
Therefore, there is a need for a higher-order mismatch-shaping DEM algorithm that does not suffer from the stability problems, the hardware complexity or other problems.